The present invention relates to electronic circuits, and, more particularly, to programmable glitch filters.
Digital circuit designs use the binary signal levels logic 0 and logic 1. These signals may also be referred to as logic LOW and logic HIGH, respectively. A glitch is an unwanted transition in the logic level (either LOW or HIGH). This effects the performance of digital circuits since storage elements (e.g., flip-flops) change their logic state on either a LOW to HIGH or HIGH to LOW logic transition. A glitch is illustrated in FIG. 1.
The most conventional method of suppressing glitches in digital circuits on printed circuit boards (PCBs), for example, is by using an RC circuit. One example of a glitch suppression mechanism including an RC circuit is shown in FIG. 2A. The step input to the RC circuit (at point X) is shown in FIG. 2B. The response of the circuit is illustrated in FIG. 2C, and the waveform at the output of the buffer (at Z) is shown in FIG. 2D. When a step input (shown in FIG. 2B) is given to the RC circuit (at X of FIG. 2A), the response of the circuit (at Y, shown in FIG. 2C) can be mathematically represented by the following equation (1):
Vo=Vi (1xe2x88x92exe2x88x92t/RC),xe2x80x83xe2x80x83(1)
where t is time in seconds, R is resistance in ohms and C is capacitance in farads.
The glitch suppression technique using an RC circuit can be employed both for positive and negative glitches. The glitch suppression mechanism for positive glitches is shown in FIGS. 3A to 3C, and the glitch suppression mechanism for negative glitches is shown in FIGS. 4A to 4C. The values of R and C are to be selected such that for maximum glitch width the response of the RC circuit does not cross the threshold of the buffer.
A waveform with positive glitch is shown in FIG. 3A. This waveform is input to the RC circuit (point X in FIG. 2A). The response of the RC circuit to the input waveform (at Y in FIG. 2A) is shown in FIG. 3B. The glitch free signal (at Z in FIG. 2A) is shown in FIG. 3C. A waveform with negative glitch is shown in FIG. 4A. This waveform is input to the RC circuit (point X in FIG. 2A). The response of the RC circuit to the input waveform (at Y in FIG. 2A) is shown in FIG. 3B. The glitch free signal (at Z in FIG. 2A) is shown in FIG. 4C.
Glitch suppression by delay elements is the most widely used glitch suppression for application specific integrated circuit (ASIC) applications. A large number of patents exist on glitch suppression using delay elements. A typical glitch suppression mechanism is discussed below with reference to figures from Japanese patent No. 4,287,512. The glitch suppression mechanism for positive glitches disclosed in the patent is shown in FIGS. 6A to 6E. The glitch suppression mechanism for negative glitches is shown in FIGS. 7A to 7E.
This prior art circuit essentially uses an SR (Set-Reset) flip-flop. The SR flip-flop is realized using two NAND gates NAND1 and NAND2. The component DELBUF acts as a delay buffer. The delay buffer delays the input signal (signal at A in FIG. 5) by a fixed amount. The delay buffer is selected such that the delay inserted by it is equal to a maximum glitch width that is to be suppressed.
FIG. 6A shows a waveform having a positive glitch. FIG. 6B shows the output of the delay buffer. The waveforms at the S and R inputs of the SR flip-flop are shown in FIGS. 6C and 6D, respectively. The output glitch free waveform is shown in FIG. 6E. FIG. 7A shows a waveform having a negative glitch. FIG. 7B shows the output of the delay buffer. The waveforms at the S and R inputs of the SR flip-flop are shown in FIGS. 7C and 7D respectively. The output glitch free waveform is shown in FIG. 7E.
A prior art programmable glitch filter from U.S. Pat. No. 5,289,060 is shown in FIG. 8. The filter includes an SR flip-flop. The output of the flip-flop Q is set to logic 1 only when S is 1 and R is 0. Q is set to logic 0 only when S is at 0 and R is at 1. When S and R are at 0, the same logic state is maintained. A logic 1 on S and R is not allowed.
A programmable delay buffer (represented as xe2x80x9cPROGRAMMABLE DELAYxe2x80x9d in FIG. 8) provides a delay which is programmable-to a pre-determined value. This block delays the input signal at A to a programmable value. The incrementally delayed outputs of the programmable delay are fed to the AND gate and the bubbled AND gate (BAND) (the inputs of this logic element are first inverted and then logically ANDed). The output of the AND gate is 1 only when all the inputs are at logic 1. The output of the BAND gate is at logic 1 only when all the inputs are at logic 0.
The glitch suppression mechanism for positive pulses is shown in FIGS. 9A to 9E. FIG. 9A shows the waveform having positive glitches. FIG. 9B shows the waveform after maximum programmed delay at In. The output of the AND gate is shown in FIG. 9C, and the output of the BAND gate is shown in FIG. 9D. The glitch free output present at Q of SR flip-flop is shown in FIG. 9E.
The glitch suppression mechanism for negative pulses is shown in FIGS. 10A to 10E. FIG. 10A shows the waveform having negative glitches. FIG. 10B shows the waveform after a maximum programmed delay at In. The output of the AND gate is shown in FIG. 10C, and the output of the BAND gate is shown in FIG. 10D. The glitch free output present at Q of the SR flip-flop is shown in FIG. 10E.
The above prior art devices all use a delay element to delay the signal. The delay signal and the original signal are compared. The output of the glitch filter is assigned to the input only when both the inputs have same value. The delay elements are implemented using buffers, and the existing glitch suppression techniques work fine for glitches of small pulse widths (i.e., tens of ns). Yet, if the glitch width is on the order of a few hundreds of microseconds or a few milliseconds, glitch suppression using the above techniques become very difficult. This is mainly because implementing a delay element to delay the signal by a few hundred microseconds may be very difficult.
An object of this invention is to obviate the above drawbacks and provide a programmable glitch filter which can suppress glitch width on the order of a few hundred microseconds or a few milliseconds.
This and other objects, features and advantages of the invention are provided by a glitch filter including storage means for storing a current state, which is the output of the filter. The output of the storage means is connected to one input of a state comparator, and the other input of the state comparator is connected to the input signal. A programmable clock delay means, which may provide a required duration independent of the technology of implementation, is connected between the state comparator and the storage means. The arrangement of the glitch filter may be such that the input signal is stored as the new current state in the storage means only if the input signal changes and then remains unchanged for the programmed duration.
The means for providing a programmable clock delay may include a counter for counting clock pulses to provide a time delay. A control input of the counter may be connected to the output of the state comparator. Further, an output of the counter may be connected to one input of a digital delay comparator. The other input of the delay comparator may receive a digital value corresponding to the maximum glitch width to be filtered. Also, an output of the delay comparator may be connected to the input of the storage means. The counter may be enabled if the input to the glitch filter is not equal to the output of the storage means, and the counter may be initialized when the input of the glitch filter is equal to the output of the storage means.
A multiplexer may be provided at the output of the storage means which also receives the input signal at an input thereof and the programmable digital value for the desired maximum glitch width at its control input. An arrangement of the multiplexer is such that when the programmed digital value is zero, the input signal is fed to the output of the multiplexer. Also, when the value is not zero, the storage means output is fed to the output of the multiplexer. The number of bits used for the counter and the digital delay comparator depends upon the desired range of programmable digital values necessary for maximum glitch width.
A method aspect of the invention for filtering glitches includes storing a current state, which is the final output, and comparing the current state with the input signal. Further, a programmable delay is enabled whenever the input signal is different from the stored current state, and the programmable delay is initialized whenever the input signal is the same as the stored current state. The method may also include making the stored current state equal to the input signal if the programmed delay is complete.
More specifically, the programmable delay may be obtained by counting clock pulses, comparing the counted clock pulses with a digital value corresponding to the maximum glitch width, and generating a signal indicating completion of programmed delay when the counted clock pulses become equal to the digital value. The counting may be enabled only if the input signal is not equal to the stored output state, and counting may be initialized whenever the input signal is equal to the stored output state. Also, the filtering of glitches may be enabled when the digital value for desired glitch width is non-zero, and it may be disabled when the digital value is zero.